Power Field-Effect Transistors (“FET”s) are required to operate properly in extreme conditions. The semiconductor industry defines “ruggedness” as the capability of the FET to withstand extreme conditions when subjected to Unclamped Inductive Switching (“UIS”). Two mechanisms cause FET failure during UIS testing. The first failure mechanism is bipolar failure, also known as active mode failure. The second failure mechanism is thermal failure, also known as passive mode failure. Bipolar failure results when an avalanche current forces the parasitic bipolar transistor within the FET into conduction. Thermal failure results when the instantaneous chip temperature exceeds a maximum temperature. At this elevated temperature, thermal regeneration or “mesoplasma” forms within the parasitic bipolar transistor within the FET and causes catastrophic thermal runaway. Both failure mechanisms result in irreparable failure.
FIG. 1 (Prior Art) is a simplified circuit diagram of an UIS test circuit 1. The UIS test circuit 1 comprises a FET under test 2, an inductor 3, a voltage source 4, and a current meter 5. The FET 2 has a gate, source and drain terminal. The source terminal of FET 2 is coupled to ground. The gate terminal of FET 2 is coupled to a test input voltage waveform Vgs. The drain terminal of the FET 2 is coupled to a first terminal of inductor 3. A second terminal of inductor 3 is couple to a first terminal of voltage source 4. A second terminal of voltage source 4 is coupled to ground. Current meter 5 measures the current flowing through FET 2. The UIS test circuit 1 applies a test input voltage waveform Vgs to the gate terminal of FET 2 and measures the resulting current flowing through FET 2.
When current flowing through an inductance is quickly switched off, the magnetic field of the inductor induces a counter electromagnetic force (“EMF”) that can generate a very high voltage across the controlling switch. Mechanical switches often have spark-suppression circuits to dissipate these high voltages without causing damage to the switch. However, when using a FET switch the high voltages generated across the FET may far exceed the rated breakdown voltage (VBR(DSS)) of the FET, thus resulting in catastrophic failure. Breakdown voltage is the maximum voltage at which the FET is guaranteed to properly operate. The voltage applied across the controlling switch can be expressed as:Vswitch=L di/dt+VDD  Eq. (1)where L is the inductance of inductor 3, and VDD is the amplitude of voltage supplied by voltage source 4. The energy absorbed by the switch may be expressed as:
                    E        =                              1            2                    ⁢                      I            0            2                    ×                      L            ⁡                          [                                                V                                      BR                    ⁡                                          (                      eff                      )                                                                                                            V                                          BR                      ⁡                                              (                        eff                        )                                                                              -                                      V                    DD                                                              ]                                                          Eq        .                                  ⁢                  (          2          )                    where, I0 is the peak current flowing through FET 2 before FET 2 is switched off, and VBR(EFF) is the voltage present across FET 2.
FIG. 2 (Prior Art) is a waveform diagram of UIS signals during switching. The input signal Vgs is set to an ON voltage level from time to to time t1. An ON voltage is a voltage level high enough to cause the FET to a conducting state. At time t1 input signal Vgs is set to an OFF voltage level. An OFF voltage is a voltage level below the ON voltage where the FET enters a non-conducting state. Input signal Vgs remains at an OFF voltage level from time t1 to t3. The current flowing through FET 2 increases from time to to time t1. At time t1 FET 2 switches off and causes an abrupt break in the drain current of FET 2. Given that the current of the inductor cannot change instantaneously, a voltage is induced on the drain of FET 2 in accordance with equation 1. The induced voltage across FET 2 may exceed the breakdown voltage of the FET 2. When the voltage across FET 2 exceeds the breakdown voltage of FET 2, an avalanche current may be induced in FET 2. The inductor forces a decreasing flow of current from time t1 to time t2. During this period, the potential across FET 2 is clamped at VBR(EFF) and the current in the inductor decays linearly from Io to zero, as is shown in FIG. 2. The inductor current decay time may be expressed as:
                              t          AV                =                  [                                                    I                0                            ×              L                                                      V                                  BR                  ⁡                                      (                    eff                    )                                                              -                              V                DD                                              ]                                    Eq        .                                  ⁢                  (          3          )                    At time t2 inductor 3 ceases to conduct current and the voltage across FET 2 falls to VDD. From time t2 to time t3 the UIS test circuit 1 is in a steady state with zero current flowing through FET 2 and constant voltage of VDD applied to the drain terminal of FET 2.
The bipolar failure effect refers to the activation and subsequent secondary breakdown of the parasitic bipolar transistor. The intrinsic diode of a FET is the collector-base junction of the parasitic bipolar transistor. Current cascading laterally through the p body region of the FET is considered responsible for the bipolar failure effect. A voltage induced by the laterally cascading current (IoRp) activates the parasitic bipolar transistor.
FIG. 3 (Prior Art) illustrates a model of the bipolar failure effect mode in the vertical FET structure. The bipolar failure effect model 2 comprises a gate terminal 7, p type body 8, n type drift layer 9, n type substrate 10, n type source region 11, lateral body resistance (RP) 12, source electrode 13, vertical body resistance (RB) 14, inherent Zener diode region 15, and parasitic bipolar transistors 16. When the voltage applied across the FET exceeds the rated breakdown voltage, an avalanche current 17 may be induced. The initial avalanche current 17 at breakdown is heavily concentrated near the inherent Zener diode region 15. Avalanche current concentrated in the inherent Zener diode region does not normally initiate bipolar action because the lateral resistance RP 12 is much greater than vertical resistance RB 14. However, as the avalanche current 17 increases, the avalanche current 17 also spreads across the p/n junction and results in avalanche currents 17 cascading laterally through the p type body region 8. These laterally cascading avalanche currents develop sufficient bias voltage across the lateral body resistances RP 12 and activate parasitic bipolar transistors 16. The bias voltage may be expressed as:VBE=IA×RP  Eq. (4)where, VBE is the bias voltage, IA is the laterally cascading avalanche current, and RP is the lateral resistance 12. Activation of the parasitic bipolar transistors 16 results in hot spotting and lowering of the turn on voltage of parasitic bipolar transistors 16. As such, thermal regeneration (also known as mesoplasma formation) occurs leading to runaway and irreversible failure.
The temperature of the FET may increase without activating parasitic bipolar transistors 16. As the FET is subjected to increasing avalanche current, the internal temperature of the FET rises dramatically. Avalanche currents cause a drastic increase in energy that must be dissipated by the FET. The calculation of the energy present in the FET as a result of avalanche current is presented in equation 2 above. The resulting energy in the FET is not easily dissipated and therefore causes the temperature of the FET to rise significantly. If the rise in internal temperature of the FET exceeds the maximum operation temperature of the FET, thermal regeneration (also known as mesoplasma formation) will occur. Thermal regeneration leads to irreversible damage generally associated with thermal runaway.
FIG. 4 (Prior Art) is a typical top view of a vertical power field effect transistor 18. The top surface of a typical vertical power FET 18 comprises a ring area 19, a gate bus area 20, an active area 21, a gate bus terminal 22, and a active area terminal 23. The active area 21 is the center area. The gate bus area 20 surrounds the active area 21. The ring area 19 surrounds the gate bus area 20. The active area 21 is where the top metal layer is connected to the body and source regions of the power FET device. The gate-bus area 20 is where the top metal layer is connected to the gate electrode so to control the gate voltage. The ring area 19, or junction termination area, allows high voltages to be sustained when operating in blocking mode.